There is currently no support for simulation of the Soft Error Mitigation Controller. Functional and timing simulation of a design including the controller will compile, but the controller will not exit the initialization state. There is no support for partial reconfiguration when using the Soft Error Mitigation Controller. Please see Chapter 9 of the Soft Error Mitigation Controller User Guide (UG764) for further information on unsupported features and limitations.
The Soft Error Mitigation Controller has been verified using production Virtex-6 FPGA devices. Use of this core on Engineering Silicon (ES) devices is not supported due to a silicon errata item regarding "Configuration Readback". The core may not work at all on ES devices, and if it does, its operation may be unreliable. Therefore, this core must not be used in ES silicon for any purpose other than evaluation. If you are using this core on an ES device for evaluation and you encounter a problem, please obtain a production device. For more information, refer to the Virtex-6 FPGA CES Errata at: http://www.xilinx.com/support/documentation/virtex-6.htm#131587.
The following devices are supported by the core for this release: