We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 37975

Virtex-5/-6 - MMCM Phase Error in clocking wizard summary page


What does "Phase Error" shown in the clocking wizard output clock summary mean?

How is it different to the peak to peak jitter?


Phase error is the phase (or time) difference between the rising edges of CLKIN and CLKFBIN. The value measured is a median value. Phase error can also be called as Phase Offset.

The variation of the above said phase (or time) difference is called phase jitter. The value is measured as peak to peak value which is called peak to peak jitter.

(It can be expected that phase error value always remains lower than peak to peak jitter value)
AR# 37975
Date 12/15/2012
Status Active
Type General Article
  • Virtex-5 SXT
  • Virtex-5 FXT
  • Virtex-5 LX
  • More
  • Virtex-5 LXT
  • Virtex-5 TXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
Page Bookmarked