AR# 38956

Aurora 8B10B v5.2 & v6.1 - Clock correction is disabled in the example design

Description

Why do I never see clock correction sequences transmitted when I use the example design?

Solution

The example design incorrectly keeps the standard_cc_module module in reset due to the incorrect polarity of the lane_up_reduce_i signal. If you invert the lane_up_reduce_i signal in the example_design module before it goes to the standard_cc_module module, this will resolve your issue.
AR# 38956
Date 03/01/2013
Status Active
Type General Article
IP