System Jitter is to take account of the substrate bounce from everything switching.
What is it? The Ground movement and analog effects on VCC, which can vary from perhaps as little as 100 ps, to as much as 1000 ps, depending on many factors but primarily how thePCB was designed and the decoupling used.
You should route the inside clockout through a DDR DFF IOB pin (any will do), and then measure the jitter on this clock.This will be the total system jitter, including the input source jitter (PERIOD ... INPUT_JITTER).
Timing constraints must then meet the period, less 1/2 the peak-to-peak value of the total system jitter. So, for example, at 3.3 ns period (300 MHz clock) with 500 ps -peak jitter, no delay can be greater than 2.8 ns; setting the period constraint AND the system jitter value performs this timing check automatically. If the slack is not there, that path is flagged with a timingerror in the verbose timing report (use the verbose to reveal all the warnings and problems).
If jitter is a problem, consider using the clock 180 or clock 270 output of a DCM (or PLL) to clock some of your logic. By using different phases of the clock, you can easily cut your system jitter in half, or more.Heavy use of fabric (like all DFF on the same BUFG) is usually the cause of jitter in the fabric.
I/Os switching tend to cause most of the system jitter due to the ground bounce in the IOB banks, which affects the overall ground of the entire chip. Selecting a different phase for some I/Os versus others is also a good way to cut down on the jitter.
Use the lowest I/O drive value that meets your requirements. If slow skew is an option, use the slow skew attribute for those I/Os that can run with a slower skew.
Overall signal integrity is the cause of jitter, so poor SI will lead to large jitter. Are all I/O signals matched to their loads? There should be no overshoot andno undershoot in a properly engineered design.Any deviation from this means more jitter.