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This Release Notes and Known Issues Answer Record is for the 7 series Integrated Block for PCI Express, first released in ISE Design Suite 13.1 and contains the following information:
For installation instructions, general CORE Generator tool known issues, and design tools requirements, see the IP Release Notes Guide.
Additional documentation for this core can be found at:
http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci-express.htm
General Information
New Features
Supported Devices
Note: For the previous versions "New Features" and "Supported Devices", see the readme.txt or version information file available with the generated core.
Known Issues
This table correlates the core version to the first ISE design tools release version in which it was included.
Version |
Vivado Tools Version |
Version |
1.11 | N/A | 14.7 |
1.10 | N/A | 14.6 |
1.9 | N/A | 14.5 |
1.8.1 | 2012.4.1 | 14.4.1 |
1.8 | 2012.4 | 14.4 |
1.7 | 2012.3 | 14.3 |
1.6 | 2012.2 | 14.2 |
2012.1 | ||
2012.1 | ||
N/A | ||
N/A | ||
N/A |
Note: For 7 series FPGA Errata, see: http://www.xilinx.com/support/documentation/7_series_errata.htm.
The following table provides known issues for the 7 series Integrated Block for PCI Express.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
(Xilinx Answer 57764) | TX de-emphasis setting is not set correctly on Lane 1 through Lane 7 in VHDL version of the core | 1.10 | Not Resolved Yet |
(Xilinx Answer 55529) | CDC (Clock Domain Crossing) Issue | 1.9 | 1.10 |
(Xilinx Answer 55909) | Designs for Artix-7 devices may not meet timing if implemented on ISE | 1.9 | Use v2.0 in Vivado |
(Xilinx Answer 55899) | The core does not link train when selecting 125mhz as reference clock frequency | 1.9 | v2.1 |
(Xilinx Answer 55537) | How do you generate the core for production Zynq devices? | 1.9 | v2.1 |
(Xilinx Answer 55508) | Provided NCSIM simulation script with the example design does not work | 1.9 | 1.10 |
(Xilinx Answer 55311) | Downstream Memory Write transactions fail in VHDL example design simulation for the core generated with 128 bit interface width | 1.9 | v2.1 |
(Xilinx Answer 54232) | (ISE 14.4/ Vivado 2012.4) - How to generate the core for Artix-7 Production Silicon | 1.8 | 1.8.1 |
(Xilinx Answer 53740) | (ISE 14.4 / Vivado 2012.4) - No Clock Output on TXOUTCLK at Cold Temperature | 1.8 | 1.9 |
(Xilinx Answer 53250) | (Vivado 2012.4) - Setup timing violation on userclk1 | 1.8 | Not Resolved Yet |
(Xilinx Answer 53251) | (ISE 14.4) - Setup timing violations on paths between ../pcie_block_i (CPU) and [../bram36_dp_bl.bram36_tdp_bl (RAM)]/ ] / [../sdp_bl.ramb36_dp_bl.ram36_bl (RAM)] | 1.8 | 2.2 |
(Xilinx Answer 53550) | 128-bit user interface with 64-bit BAR simulation is not working - malformed packet sent by the Root Port Simulation Model (DSPORT) |
1.7 | 2.1 |
(Xilinx Answer 53056) | (ISE 14.3) ERROR:Xst:2927 - Source file ../source/PCIe_portion_pipe_clock_tandem.vhd" does not exist | 1.7 | Not Resolved Yet |
(Xilinx Answer 52968) | (Vivado 2012.3) Simulation warning in Cadence IES "ncelab: *W,CSINFI: implicit wire has no fanin ({*Name Protected*})" | 1.7 | 1.8 |
(Xilinx Answer 52447) | (Vivado 2012.3) userclk2 incorrectly constrained in XDC file when generating x8Gen2 core for KC705 board | 1.7 | 1.8 |
(Xilinx Answer 50683) | (ISE 14.3/Vivado 2012.3) MSI Per Vector Masking Capability Support | 1.7 | Not Resolved Yet |
(Xilinx Answer 51448) | 7 Series FPGA GTP Transceivers - RX Termination Use Modes | 1.6 | Not Resolved Yet |
(Xilinx Answer 51135) | The core does not link up on Z77(Ivy Bridge) platform | 1.6 | 1.9/2.0 |
(Xilinx Answer 51381) | UCF in the example design has a TIG constraint for 125 MHz clock even for Gen1 mode | 1.4 | 1.7 |
(Xilinx Answer 51285) | (Vivado 2012.2) - Does not link train with XCV72000T devices | 1.6 | 1.7 |
(Xilinx Answer 50692) | (ISE 14.1/Vivado 2012.1) - The core may truncate some DLLPs/TLPs during the process of going into Recovery | 1.4 | Not Resolved Yet |
(Xilinx Answer 50944) | (ISE 14.2/Vivado 2012.2) - Tandem PCIe and Tandem PROM support | 1.6 | 1.7 |
(Xilinx Answer 50835) | (ISE 14.2/Vivado 2012.2) - VHDL simulation support for Root Port Configuration | 1.6 | Not Resolved Yet |
(Vivado 2012.1) - x8 Link Width not supported on Artix devices | 1.6 | ||
(ISE 14.1) - Core generation for XC7V1500T and XC7V2000T devices | |||
(Vivado 2012.1) - VHDL Root Port Configuration Support | 1.6 | ||
(ISE 14.1/Vivado 2012.1) -VHDL Simulation Support in Endpoint Configuration | |||
(ISE 14.1) - Incorrect Completion Packets Generation for Interface Width 128-bit with Configuration Other than x8Gen2 | |||
(ISE 14.1 / Vivado 2012.1) - Timing Violations in Certain IP Configurations | |||
(Vivado 2012.1) - Core Configurations Other than x1Gen1 (64-bit) and x1Gen2 (64-bit) not Supported | |||
(Vivado 2012.1) - VHDL Support in Endpoint Configuration | |||
(Vivado 2012.1) - Root Port Configuration Support | |||
Enabling OOB Clock Mode | |||
ISIM example script fails to compile when using VHDL | |||
VHDL Flow Does Not Produce VHDL for MGT Wrapper Files | Not Resolved Yet | ||
(Xilinx Answer 44681) | Is Synplify supported? | ||
Signals cfg_pm_halt_l1, cfg_pm_force_state[1:0] seem to imply APSM L1 is supported | |||
VHDL Simulation Results in "Failure: Rx Simulation Timeout" | |||
How to target the Kintex-7 Integrated Block Wrapper to the KC705 boards | |||
Blocks on left side may have unpredictable behavior when using ISE 13.2 | |||
Selectable Devices That Are Not Supported. | |||
sys_reset_n does not have a pin location constraint. | |||
Missing BRAM LOC constraints in UCF. | |||
Pin to Pin Skew timing constraint failure targeting -2L | |||
Link Training fails due to incorrect MGT attributes | |||
x8 Gen 1 and x4 Gen 2 designs using 128-bit interface do not simulate | |||
Simulation link up takes too long | |||
RECRC Check and Trim TLP Digest overlap. | |||
MSI-X Table Size Field in Customization GUI Should Be Entered as Decimal Number | |||
A Version 1.1 Core Does Not Implement in ISE Design Suite 13.2 Due to Port Changes on GTXE2_COMMON |
Revision History
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
51901 | Virtex-7 FPGA VC709 Connectivity Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
45382 | Virtex-7 FPGA VC707 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
45934 | Kintex-7 FPGA KC705 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
51900 | Artix-7 FPGA AC701 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
51233 | Virtex-7 FPGA VC707 Evaluation Kit - Board Debug Checklist | N/A | N/A |
50079 | Kintex-7 FPGA KC705 Evaluation Kit - Board Debug Checklist | N/A | N/A |
54139 | Artix-7 FPGA AC701 Evaluation Kit - Board Debug Checklist | N/A | N/A |
54355 | Virtex-7 FPGA VC709 Connectivity Kit - Board Debug Checklist | N/A | N/A |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
40595 | 7 Series Integrated Block for PCI Express - x8 Gen 1 and x4 Gen 2 designs using 128-bit interface do not simulate | N/A | N/A |
41271 | 7 Series Integrated Block for PCI Express - RECRC Check and Trim TLP Digest overlap | N/A | N/A |
43347 | Kintex-7 FPGA Initial Engineering Sample (ES) - Known Issues Master Answer Record | N/A | N/A |
AR# 40469 | |
---|---|
Date | 10/16/2014 |
Status | Active |
Type | Release Notes |
IP |
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