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AR# 41286

System Generator - Multi Cycle-True Islands and their clocks must be contain only 1 subsystem level at the top-level


Multiple hierarchical levels of Subsystems which require multi clock domains will not be implemented correctly as only 1 Multiple Subsystem Generator token can be used at the top-level of the design.


As stated in the help document of the Multiple Subsystem Generator, the Xilinx Multiple Subsystem Generator block wires two or more System Generator designs into a single top-level HDL component that incorporates multiple clock domains.

If the tools find the Multiple Subsystem Generator block, then it will recognize the subsystems at the hierarchy as multiple cycle-true islands. 

The Multiple Subsystem Generator will create a separate clock port for each subsystem that was generated. 

However, if the tools does not find the Multiple Subsystem Generator block and only finds the System Generator clock, it will only generate a clock for the block.


This limitation can be worked around by ensuring all subsystems requiring multiple clock domains are contained at the top level of the hierarchy.

There is no plan to modify ISE Sysgen to incorporate the ability to have more than 1 "Multiple Subsystem Generator" tokens at different hierarchical levels.

As the "Multiple Subsystem Generator" block is not supported in Vivado Sysgen, this answer record does not apply to Vivado Sysgen.


AR# 41286
Date 12/01/2014
Status Active
Type General Article
  • System Generator for DSP
  • ISE Design Suite
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