We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 41537

13.1 XST - ERROR:HDLCompiler:40 - "sourcefile.vhd" Line XX: my_entity is not a entity


I am trying to run synthesis using XST-2 on code similar to the following:

my_instance : entity my_entity port map(in_port =>in_port ...

 I receive the following error:

ERROR:HDLCompiler:40 - "sourcefile.vhd" Line XX: my_entity is not a entity

 This code works fine with XST, but not XST-2.


This is a bug in the new parser that XST-2 uses.  

The issue is fixed in ISE 13.2 under a run-time flag.  

Please do either of the following to enable the fix, the fix will not be available by default.

1. Set the environment variable XST_VHDL_IMPLICIT_WORK:


2. Include the following lines in the XST script file:

set -checkcmdline no 
set -vhdl_implicit_work_lib 1

For ISE releases prior to 13.2, the workaround is to write your code like the below:


my_instance : entity work.my_entity port map(in_port =>in_port ...


The difference here is that my_entity is identified as being found in the "work" library.

AR# 41537
Date 09/10/2014
Status Active
Type General Article
Page Bookmarked