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AR# 41821

Design Advisory for Virtex-6 BitGen Option Change Can Cause Configuration Failures for Bit Files Generated in 13.2 Where 13.1 Files Worked

Description

The Virtex-6 default BitGen option, "-g Next_Config_Addr" has changed. 

Effective in the 13.2 ISE software, the default value for this BitGen option changed from an 8-digit hex value to "None." 

If you do not change this default configuration option when migrating from 13.1 to 13.2, this can cause configuration failures over JTAG and other configuration interfaces.

In the iMPACT tool, you will see "Configuration Failed" in the Boundary Scan Window and the following informational messages in the console:

INFO:iMPACT:2218 - Error shows in the status register, release done bit is NOT 1.
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0000 0000 0000 0000 0000 0000 0000 0000

In the ChipScope Analyzer, DONE will go high, but the device is not configured and you do not see a failure.

Instead, the following informational messages are printed in the console:

COMMAND: configure 1 "path\filename.bit" 0 import_inserter_cdcpath\filename.cdc doAuto
INFO: Found 0 Core Units in the JTAG device Chain.
INFO: If cores were expected to be found, see Answer Record 19337.

In the ChipScope tool, after checking the configuration status you will see DONE high, but GHIGH low. 

This indicates that no configuration data was loaded. 

The status will appear as follows:

Bits [31 ..0]: 0000 0001 1100 0000 0111 1101 0111 1100
Bit 31:0 EFUSE_BUSY
Bit 30:0
Bit 29:0 BAD_PACKET
Bit 28:0 HSWAP_EN
Bit 27:0
Bit 26:0 BUS_WIDTH
Bit 25:0 BUS_WIDTH
Bit 24:1 FS
Bit 23:1 FS
Bit 22:1 FS
Bit 21:0
Bit 20:0 STARTUP_STATE
Bit 19:0 STARTUP_STATE
Bit 18:0 STARTUP_STATE
Bit 17:0 MON_OT_ALARM
Bit 16:0 SEC_VIOLATION
Bit 15:0 ID_ERROR
Bit 14:1 DONE
Bit 13:1 RELEASE_DONE
Bit 12:1 INIT_B
Bit 11:1 INIT_COMPLETE
Bit 10:1 MODE M2
Bit 9:0 MODE M1
Bit 8:1 MODE M0
Bit 7:0 GHIGH_B
Bit 6:1 GWE
Bit 5:1 GTS_CFG_B
Bit 4:1 EOS
Bit 3:1 DCI_MATCH
Bit 2:1 DCM_LOCK
Bit 1:0 PART_SECURED
Bit 0:0 CRC_ERROR

Solution

The default -g next_config_addr setting in ISE 13.1 was 0x00000000 and this allowed JTAG to work because an IPROG command was not inserted properly.

BitGen ignored the 8-digit hex value specified. 

This is explained in (Xilinx Answer 43011).

Beginning in the 13.2 ISE software, the Virtex-6 -g Next_Config_addr "Starting Address for Fallback Configuration" has a default value of "None." 

This setting allows configuration to work without considering Multiboot image addressing because the IPROG command is not inserted into the bitstream.

In the 13.2 ISE software, configuration on any interface might fail if you have the old 12.4 or 13.1 ISE software default value of 0x00000000 or any non-zero address specified because the IPROG command will be inserted into the bit file with these settings.

Note: For existing Virtex-6 projects, you need to go back in and manually set the properties dialog box to the default value of "None."

In the Project Navigator, right click "Generate Programming File" and select "Configuration Options" in the Process Properties dialog box.

The incorrect value of 0x00000000 will still be shown for existing designs. 

Replace this value with "None."

If no other options on this page have changed, you can select the "Default" button to populate "None" automatically in the "Starting Address for Fallback Configuration" field with all of the other default property values.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34565 Design Advisory Master Answer Record for Virtex-6 FPGA N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34565 Design Advisory Master Answer Record for Virtex-6 FPGA N/A N/A
AR# 41821
Date Created 06/15/2011
Last Updated 10/13/2014
Status Active
Type Design Advisory
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
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Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • More
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
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Boards & Kits
  • Platform Cable USB
  • Platform Cable USB-II
  • Virtex-6 FPGA Broadcast Connectivity Kit
  • More
  • Virtex-6 FPGA Connectivity Kit
  • Virtex-6 FPGA Embedded Kit
  • Virtex-6 FPGA ML605 Evaluation Kit
  • Virtex-6 FPGA ML623 Characterization Kit
  • Xilinx Parallel Cable IV
  • Less