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AR# 42123

Virtex-6 FPGA Integrated Block Wrapper v1.7 for PCI Express - Linkup failure in Simulation with PIPERXVALID going undefined

Description

Version Found: v1.6, v1.7

Version Resolved and other Known Issues: See (Xilinx Answer 40446).

Description:

In simulation, the PCI express core might not complete link training and will enter ltssm state 0x6 (Pre_Send_EIOS).

NOTE: "Version Found" refers to the version the problem was first discovered.
The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Solution

To work around this issue, modify gtx_rx_valid_filter_v6.v(hd) as follows:

For Verilog:

1. Open //source/gtx_rx_valid_filter_v6.v
 
2. Change the following code from:

wire awake_see_com_0 = GT_RXVALID & (gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_COM));
wire awake_see_com_1 = GT_RXVALID & (gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_COM));

to:

wire awake_see_com_0 = gt_rxvalid_q & (gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_COM));
wire awake_see_com_1 = gt_rxvalid_q & (gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_COM));

For VHDL:

1. Open //source/gtx_rx_valid_filter_v6.vhd

2. Change the following code from:

awake_see_com_0<= GT_RXVALID and (gt_rxcharisk_q(0) and
to_stdlogic(gt_rxdata_q(7 downto 0) = EIOS_COM));

awake_see_com_1<= GT_RXVALID and (gt_rxcharisk_q(1) and
to_stdlogic(gt_rxdata_q(15 downto 8) = EIOS_COM));

to:

awake_see_com_0<= gt_rxvalid_q and (gt_rxcharisk_q(0) and
to_stdlogic(gt_rxdata_q(7 downto 0) = EIOS_COM));

awake_see_com_1<= gt_rxvalid_q and (gt_rxcharisk_q(1) and
to_stdlogic(gt_rxdata_q(15 downto 8) = EIOS_COM));

Revision History
4/13/2012 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40446 Virtex-6 FPGA Integrated Block Wrapper v1.7 for PCI Express - Release Notes and Known Issues N/A N/A
AR# 42123
Date Created 04/17/2012
Last Updated 10/20/2014
Status Active
Type Known Issues
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )