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AR# 42187

Aurora 8b/10b - Spartan-6 GTP line rates extended


The Spartan-6 FPGA GTP line rates have been extended from these rates:

Range 1: 0.6 Gb/s to 0.81 Gb/s
Range 2: 1.2 Gb/s to 1.62 Gb/s
Range 3: 2.45 Gb/s to 3.125 Gb/s

to these rates:

Range 1: 0.6 Gb/s to 0.81 Gb/s
Range 2: 0.94 Gb/s to 1.62 Gb/s
Range 3: 1.88 Gb/s to 3.125 Gb/s

The Aurora 8B10B v5.2 core cannot be generated with these extended line rates.


Aurora 8B10B v6.2 core released in ISE 13.1 software does have Spartan-6 FPGA GTP extended line rate related updates. The easiest way to work around this is by upgrading to the v6.2 core. This version has the AXI4 interface. If it is required for the core to have the local link interface, the workaround below can be used to create a v5.2 core with the extended line rates:

1. Generate the Aurora 8B10B v6.2 core with
a. Required Line Rate
b. Required GT REFCLK
c. Same component name as of Aurora 8B10B v5.2 core

2. Copy the following files from generated Aurora 8B10B v6.2 core to Aurora 8B10B v5.2 core dir:
a. <component name>/example_design/<component name>_example_design.ucf
b. <component name>/example_design/gt/<component name>_tile.v[hd]
c. <component name>/example_design/gt/<component name>_transceiver_wrapper.v[hd]
d. <component name>/example_design/clock_module/<component name>_clock_module.v[hd]
e. <component name>/simulation/demo_tb.v[hd]

3. Rename the copied file name from <component name>/example_design/gt/<component name>_tile.v[hd] to <component name>/example_design/gt/<component name>_ transceiver_tile.v[hd]

Now Aurora 8B10B v5.2 core is updated with Spartan-6 FPGA extended line rate changes
AR# 42187
Date 12/15/2012
Status Active
Type General Article
  • Aurora 8B/10B
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