AR# 42195: MIG v3.7 Virtex-6 DDR2/DDR3 - For ECC enabled designs, app_correct_en is not driven properly and ECC is not working
MIG v3.7 Virtex-6 DDR2/DDR3 - For ECC enabled designs, app_correct_en is not driven properly and ECC is not working
For ECC enabled designs, single-bit errors are being detected but not corrected. Why is ECC correction not occurring?
Port app_correct_en is an active High signal and is used to correct the data bits when there are data bit errors. In MIG v3.7 and previous releases, this port resides in memc_ui_top module only and was left unconnected when ECCwas enabled. This results in the ECC correction logic being trimmed out during synthesis and therefore no correction occurs.
This is fixed in the ISE 13.2 softwarerelease inMIG v3.8, as app_correct_en is tied to '1' in the memc_ui_top module in order to always correct single bit errors. To work around this in previous versions of MIG the user must manually modify the RTL by tying app_correct_en to '1' in the memc_ui_top module.