This Release Notes and Known Issues Answer Record is for the Memory Interface (MIG) v3.9 release in the ISE Design Suite 13.3 and contains the following information:
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide.
The MIG Virtex-6 and Spartan-6 v3.9 products are available through the ISE Design Suite 13.3.
For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA Memory Controller Block (MCB), see the following user guides:
For a list of supported memory interfaces and frequencies for Virtex-6 FPGA, see the following documentation:
For general design and troubleshooting information on MIG, see the Xilinx MIG Solution Center at (Xilinx Answer 34243)
UG406 - Added more information in AXI addressing section
(Xilinx Answer 35750) MIG v3.4-v3.8 Virtex-6 QDRII+ - Why is the QVLD signal left unconnected?
Custom part selection range for Row Address is restricted to a maximum value of 15 for DDR3 SDRAM, which is the same as the MCB allowed maximum value