When a multi-lane application requires a TX/RX buffer bypass, you must use a manual phase alignment.
The steps for the manual phase alignment are available in (UG476) 7 Series FPGAs GTX Transceivers User Guide.
In addition, you must use the workaround below to enable the manual alignment mode in the Kintex-7 GTX Initial ES silicon.
Note: You do not need to perform this work-around if you are using v1.5 of the 7 Series FPGAs Transceiver Wizard in ISE Design Suite 13.3.
PCS_RSVD_ATTR (Reg 0x06F) needs to toggle from 0 to 1 after completion of GTTXRESET, and before the manual alignment procedure.
In other words, TXRESETDONE is going high in response to GTTXRESET being asserted.
PCS_RSVD_ATTR (Reg 0x06F) needs to toggle from 0 to 1 after completion of GTRXRESET, and before the manual alignment procedure.
In other worlds, RXRESETDONE is going high in response to GTRXRESET being asserted.
NOTE: These bits need to toggle from 0 to 1, so you cannot statically set them in the UCF for the Initial ES silicon.