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AR# 43950

14.7 Timing - Does BUFG have a minimum frequency specification?

Description

I receive the following Component Switching Limit violation during timing analysis.

Is this 1 MHz minimum frequency specification on BUFG a valid one?

Component Switching Limit Checks: TS_fpga13_clk_rst_1_clk_rmii_reg_ = PERIOD TIMEGRP  "fpga13_clk_rst_1/clk_rmii_reg" 0.5 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: -1000.000ns (max period limit - period)
  Period: 2000.000ns
  Max period limit: 1000.000ns (1.000MHz) (Tbcper_I)
  Physical resource: fpga13_clk_rst_1/BUFG_clk_rmii/I0
  Logical resource: fpga13_clk_rst_1/BUFG_clk_rmii/I0
  Location pin: BUFGCTRL_X0Y26.I0
  Clock network: fpga13_clk_rst_1/clk_rmii_reg

Solution

The 1 MHz minimum frequency specification on BUFG is a coding requirement only, you can safely ignore this violation and BUFG can run below 1MHz.
AR# 43950
Date Created 09/06/2011
Last Updated 02/17/2015
Status Active
Type General Article
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