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AR# 44121

MIG 3.61 Virtex-5 DDR2 - Can I connect CS pin of DDR2 to ground?


Can I connect the CS pin of DDR2 to ground and leave the CS pin on the FPGA floating?


No, this is not supported for DDR2 SDRAM on Virtex-5 because the Address/Control signals (except CS) are asserted for two clock cycles of the DDR2 SDRAM, while the CS signal is only asserted for one. This is because the Address/Control signals (except CS) are in the CLKDIV domain, which is half the clock frequency of the DDR2 SDRAM. If CS is tied to GND, then two continuous read/write commands will be asserted and sampled by the DDR2 SDRAM, which will cause calibration failures. For this reason, the CS pin must be connected to CS on the FPGA.
AR# 44121
Date 12/15/2012
Status Active
Type General Article
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
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