Version Found: 1.00.a
Version Resolved and other Known Issues: see (Xilinx Answer 44969)
The AXI Bridge for PCI Express provides an AXI4-lite interface to access the bridge's control registers. When an incoming write transaction is received by the AXI4-lite Control Interface of the bridge, the write response channel responds with a SLVERR if the register is read only.
This is a known issue with the AXI4-lite Control Interface. Although the registers are Read Only, the write response channel should respond with OKAY instead of SLVERR.This issue is resolved in revision v1.01.a of the bridge.
11/30/2011 - Initial Release