There is an issue with the DivGen 4.0 block Latency field. The workaround is to run simulation to determine the correct latency value.
For System Generator for DSP Release Notes from other versions, see (Xilinx Answer 29595).
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 29595 | Xilinx DSP Tools, System Generator for DSP, and AccelDSP Synthesis Tool - Release Notes and Known Issues | N/A | N/A |
| AR# 45516 | |
|---|---|
| Date | 05/20/2012 |
| Status | Active |
| Type | Known Issues |
| Tools |
|