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AR# 45916

Virtex-5 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.8 - PhysDesignRules error during MAP when using SGMII or 1000BASE-X modes

Description

When targeting Virtex-5 LXT non-Q grade parts and using SGMII or 1000BASE-X, the example design results in the following error during MAP:

ERROR:PhysDesignRules:2270 - Block v5_emac_ll/v5_emac_block_inst/GTP_DUAL_1000X_inst/GTP_1000X/tile0_rocketio_wrapper_i/gtp_dual_i (GTP_DUAL_X0Y2) needs GTP_DUAL_X0Y1 instantiated: When using a GTP/GTX with a REFCLK coming from an IBUFDS element near another GTP/GTX and forwarding that clock using dedicated routing, each GTP in between the source and destination must be instantiated in the correct manner (See AR 33473).
If you don't instantiate these other GTP tiles the software tools will route the REFCLK correctly, but the design may not work in hardware.

Solution

This error is due to non-optimal placement of the GT reference clock. 

The error can be resolved by changing:

INST "MGTCLK_N" LOC = "AF3";
INST "MGTCLK_P" LOC = "AF4";

To:
 

INST "MGTCLK_N" LOC = "Y3";
INST "MGTCLK_P" LOC = "Y4";

This issue will be fixed in version 1.8 rev1 of the core. 

The rev1 patch update is available for download for the ISE 13.x software in (Xilinx Answer 40632).  

Starting in ISE 14.1 tools, this version of the core will be included in the CORE Generator software.

AR# 45916
Date Created 01/24/2012
Last Updated 09/17/2014
Status Active
Type General Article
IP
  • Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper