AR# 46513


7 Series FPGA Design Assistant - Designing Block RAM and FIFO structures in 7 Series FPGAs


This Answer Record provides information on how to use the block RAM and FIFO blocks in the7 Series FPGA fabric.

NOTE: This Answer Record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 Series devices. Whether you are starting a new design with 7 Series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.


The built in block RAM and FIFO primitives in the 7 SeriesFPGA can be used to implement RAMs, ROMs, and FIFO blocks for a design. The block RAM and FIFO are optimized for performance and allow you to implement a RAM, ROM, or FIFO block in a design without requiring large amounts of fabric resources from slice logic.

The7 Series FPGAs Memory Resources User Guide (UG473) provides additional details on the block RAM and FIFOs. It is recommended that you read through the user guides to familiarize yourself with its use and how they can be used in your design:

In addition, the following answer records are useful in providing details on different ways to implement block RAMs and FIFO blocks in your code:
(Xilinx Answer 46515) - How to infer the use of Block RAM and FIFO primitives in your HDL code
(Xilinx Answer 46516) - Using block RAM CORE Generator and FIFO CORE Generator to setup the blocks for use in HDL code

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AR# 46513
Date 12/15/2012
Status Active
Type General Article
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