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AR# 46649

AXI Bridge for PCI Express - Spartan-6 32-bit inteface AXI Initiated Write Request Creates Malformed TLP

Description

Version Found: 1.02.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

When using the 32-bit interface available only on the Spartan-6 device, a 1 DW write initiated from the AXI side of the bridge will result in a a PCIe Memory Write TLP, where the first dword byte enables and the last dword byte enable are the same. This is not allowed by the PCIe specification because a packet of 1 DW or less should have the last byte enable field set to "0000".

Solution

This issue is fixed in v1.03a which will be released in ISE 14.1 software.Prior to ISE 14.1 release, if this issue is a concern please open a case with Xilinx support and refer to this answer record. If the link partner device is checking the byte enable fields this could result in a fatal error condition. To work around this issue, fatal error reporting could be disabled in the link partner device if allowed by the system.

Revision History
03/05/2012 - Initial Release

NOTE:The "Version Found" columnlists the version in which the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 46649
Date Created 03/02/2012
Last Updated 05/20/2012
Status Active
Type Known Issues
IP
  • AXI PCI Express (PCIe)