This Answer Record provides guidance on creating a design for the Spartan-6 FPGA.
NOTE: This Answer Record is part of the XilinxSpartan-6 FPGA Solution Center (Xilinx Answer 44744).The XilinxSpartan-6 FPGASolution Center is available to address all questions related toSpartan-6 devices.Whether you are starting a new design withSpartan-6 FPGA or troubleshooting a problem, use theSpartan-6 FPGA Solution Center to guide you to the right information.
When designing for the Spartan-6 FPGA, review the Application Notes and Intellectual Property (IP)to determine if there are any which can be used for the application you are targeting.
Spartan-6 FPGA Application Notes:
For design areas not covered by IP or Application Notes, the following answer records provide guidance on how to move forward with a Spartan-6 FPGA design:
(Xilinx Answer 46744) - Designing clocking structures in Spartan-6 FPGAs
(Xilinx Answer 46745) - Designing configurable logic structures in Spartan-6 FPGAs
(Xilinx Answer 46740) - Designing Block RAM and FIFO structures in Spartan-6 FPGAs
(Xilinx Answer 46742) - Designing for I/O,PCIe, Memory Controller, and DSP in Spartan-6 FPGAs