AR# 46901


Vivado/PlanAhead - What does it mean if a source file is listed under the Unreferenced folder in the PlanAhead hierarchy?


When I open a project in Vivado IDE or PlanAhead, I find that one of the source files (e.g. .vhd/.v) modules was placed in the Unreferenced folder.

Why did this happen?


The hierarchical sources view (HSV) feature in Vivado IDE and PlanAhead(version 13.3 and later) shows the module/instance based hierarchical relation between the source files in a project.

The "Unreferenced" file group that you see is related tothe HSVfeature.

This hierarchical source view feature supports the following three update modes:

  1. In the first mode (default), called "Automatic" for short, as you add source files to a PlanAhead project, as well as subsequently edit those source files, PlanAhead tries to figure out the best "top" to use for the design and uses it by default (unless you selected a different "top", in which case it is retained). At the same time, based on the current "top", PlanAhead figures out which source files in the project are under the sub-tree for the current top, orders them automatically from lowest level to highest level, and finally send this ordered list of files along with the determined "top" to synthesis and simulation tools. During this computation, any files that PlanAhead finds to be NOT under the current top's sub-tree are considered to be "outside the active hierarchy," and by default are NOT sent for synthesis and simulation compilation.These are the sources that show up under the "Unreferenced" folder in the Libraries and Compile order tabs, since they are not directly or indirectly referenced in the current design, given the selected top.
  2. The second (as well as third) mode provides full user control over the automatic behavior described above.In this mode, called "Display Only" for short, the hierarchical relationship of sources is shown to the user - but no automatic computation of file ordering is done, and all files are sent for synthesis and simulation in the order specified by the user.
  3. Under the third mode, no hierarchical relationship of sources is computed or displayed to the user, and they have full control over which top to use and the file order to use for synthesis/simulation.

Going back to the first mode, which is default, here is a simple example. Lets say my design hierarchy is as shown below:

top1 (top1.v) |
|-- child1 (child1.v)
|-- grandchild1 (gchild1.v)top2 (top2.v)
|-- child2 (child2.v) |
|-- grandchild2 (gchild2.v)

In this project, we essentially have two independent SETS of design sources, which two potential top candidates. If we select top1 as our "top", then top2.v, child2.v and gchild2.v becomes "unreferenced" and the only files that are used for synthesis and simulation are: gchild1.v, child1.v and top1.v, and they are sent to the compilers in this "bottom up" order.

If the above explanation does not apply, please right click the source and select the source properties to verify that the file Type has not been set to unknown.
Also verify that the module names and ports match with the instantiating source file.

In many cases, the unreferenced status is due to a syntax error in the HDL code that prevents thehierarchy from being parsed and displayed as expected. Users should use the "Messages" tab to check for parsing errors. For example, a user may look in the messages tab, under the "Analysis Messages" group, and find an explicit errors mentioning what went wrong, and allow them to directly click on the error messages to cross-probe to the HDL file directly, close to where the actual error is.

AR# 46901
Date 01/23/2013
Status Active
Type General Article
People Also Viewed