| Signal | Description |
| phy_debug[0] | IDLE2 selected |
| phy_debug[1] | mode 1x |
| phy_debug[2] | IDLE1 selected |
| phy_debug[3] | port initialized |
| phy_debug[4] | rx lane r |
| phy_debug[5] | gtrx chanbonden |
| phy_debug[9:6] | 0 |
| phy_debug[13:10] | gtrx chanisaligned |
| phy_debug[29:14] | gtrx chariscomma |
| phy_debug[33:30] | gttx inhibit |
| phy_debug[34] | gtrx reset req |
| phy_debug[35] | Nxlanes aligned |
| phy_debug[36] | Nxlanes rdy |
| phy_debug[37] | 1x mode detected |
| phy_debug[41:38] | init state |
| phy_debug[42] | out of sync |
| phy_debug[95:43] | 0 |
| phy_debug[96] | rfr sent |
| phy_debug[97] | lreq sent |
| phy_debug[98] | pna sent |
| phy_debug[99] | pr sent |
| phy_debug[100] | lresp sent |
| phy_debug[101] | mce sent |
| phy_debug[102] | pa sent |
| phy_debug[103] | sent init cs |
| phy_debug[104] | send lreq |
| phy_debug[105] | link reset |
| phy_debug[159:106] | 0 |
| phy_debug[160] | send pna |
| phy_debug[161] | pna detect |
| phy_debug[162] | send pr |
| phy_debug[163] | pr detect |
| phy_debug[164] | output error stop |
| phy_debug[165] | output retry stop |
| phy_debug[166] | input error stop |
| phy_debug[167] | input retry stop |
| phy_debug[191:168] | 0 |
| phy_debug[196:192] | cause field for outgoing PNAs |
| phy_debug[197] | output fatal error detect |
| phy_debug[198] | output recoverable error detect |
| phy_debug[199] | input retry detect |
| phy_debug[200] | input recoverable error detect |
| phy_debug[201] | OLLM RXin packet |
| phy_debug[202] | OLLM RXframing sop |
| phy_debug[203] | OLLM RXframing eop |
| phy_debug[204] | OLLM RXframing discontinue |
| phy_debug[223:205] | 0 |
Note: Please connect the above signals only if it is absolutely necessary. Connecting any of these will have a negative impact on timing closure.
Revision History
04/14/2012 - Initial Release
| AR# 47191 | |
|---|---|
| Date | 05/16/2012 |
| Status | Active |
| Type | Documentation Changes |
| IP |
|