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AR# 47202

Soft Error Mitigation Controller - Vivado 2012.1: How to generate and implement the Example Design

Description

Version Found: v3.2
Version Resolved and other Known Issues: See (Xilinx Answer 44541).

This article describes how to generate and implement the Soft Error Mitigation core example design with Vivado 2012.1. It also includes instructions to create the error replace and classification files if those options are enabled.

Solution

Step 1 - Create a New Project

Launch Vivado and create a new project in any directory. In order to implement the example all the way through BitGen, pin locations are needed for the SEM example design ports. These instructions include pin locations for the XC7V485T-2FFG1761 orXC7K325T-2FFG900, so target one of these two devices in order to fully implement the design. If another device is chosen, pin locations will have to be added to the xdc file in order to complete BitGen and run the makedata.tcl file. The new project will look like the following:

Figure 1
Figure 1

Step 2 - Customize IP

Select the IP Catalog in the left side menu; then, under "FPGA Features and Design," select the "Soft Error Mitigation" IP.

Figure 2
Figure 2

For purposes of this example, enable the following options:

  • Component name: sem_v3_2_0
  • Error injection: Enabled
  • Error injection shim: Pins
  • Error correction: Enabled
  • Error correction method: Replace
  • Error classification: Enabled
  • Controller clock frequency: 8 MHz
Figure 3
Figure 3

Step 3 - Generate IP

After customizing the IP, right click on the sem_v3_2_0.xci file under Design Sources and select Generate.

Figure 4
Figure 4

Select "All" when asked to "Choose Targets to Generate." Note that the SEM IP cannot be simulated, although a design including the core can be simulated. Checking the "testbench" option does not produce any additional files. See the Product Guide for more information regarding simulation.

Figure 5
Figure 5

The instantiation template, if needed, can be found under the IP Sources tab as shown in the figure. To find the instantiation template in the generated directories, go to:

< project >/< project >.srcs/sources_1/ip/< component_name >/< component_name >.v[eo/ho]

In this example, it would be:
/project_1/project_1.srcs/sources_1/ip/sem_v3_2_0/sem_v3_2_0.veo

Figure 13
Figure 13

Step 4 - Generate the Example Design

The example design is not generated by default. The example design is generated by user request and is opened in a new instance of Vivado. This allows users to view and modify the example of various cores being usedwithout touching their own design. To generate the example design, rightclick on the sem_v3_2_0.xci file under Design Sources and select "Open IP Example Design."

Figure 6
Figure 6

A box will open asking where to put the example design. By default, ituses the current project directory. Select OK to generate the example design.

Figure 7
Figure 7

A new instance of Vivado will open showing the example design under the Design Sources window. Notice that the core is still there in the form of the "xci" file, but is no longer the top level of the design as in the other Vivado instance where the core was originally generated.

Figure 8
Figure 8

Step 5 - Add pin locations to the xdc file

The generated example design's xdc file does not include pin locations. Select pin locations appropriate for the device. If theXC7V485T-2FFG1761 orXC7K325T-2FFG900 are targeted, the pin locations are available in (Xilinx Answer 47291). Edit the XDC file located in the Design Sources window under constraints and add the pin locations.

Figure 9
Figure 9

Step6 - Run Synthesis and Implemenation

Synthesis and simulation can be run separately by clicking on the appropriate option in the left side menu, or can be run at once by just choosing "Run Implementation." Once implementation completes, the following box will pop up. Click Cancel and move to Step 7 to set needed bitstream generation options before generating the bitstream.

Figure 10
Figure 10

Step7 - Generate the Bitstream

In this example, since error classification and correction by replace options are enabled,the *.ebc and *.ebd files need to be generated along with the bitstream. Select Bitstream Settings from the lefthand menu and enter "-g essentialbits:yes" in the "More Options" field.

Figure 11
Figure 11

Select OK and then create the bitstream by selecting "Generate Bitstream" in the left side menu. The *.ebc and *.ebd files are located in the directory:

< project >/example_project/< component_name >.runs/impl_1/

For this example it is:
./project_1/example_project/sem_v3_2_0.runs/impl_1/sem_example.ebc
./project_1/example_project/sem_v3_2_0.runs/impl_1/sem_example.ebd


Step 8: Create the classification and replacement files

The classification and replacement files are generated using the makedata.tcl file included in the generated core's source files. At a terminal prompt, go to the directory containing the ebc and ebd files generated in Step 7. Depending on which options are enabled, the following command generates the necessary files. These examples show the general path and the specific instances used in this example flow.

If classification and correction by replace are enabled (used in the example outlined in these steps):

xtclsh ../../< component name >.srcs/sources_1/ip/< component name >/< component name >/implement/makedata.tcl -ebc < ebc filename > -ebd < ebd filename > datafile

xtclsh ../../sem_v3_2_0.srcs/sources_1/ip/sem_v3_2_0/sem_v3_2_0/implement/makedata.tcl -ebc sem_example.ebc -ebd sem_example.ebd datafile

If correction by replace is enabled:

xtclsh ../../< component name >.srcs/sources_1/ip/< component name >/< component name >/implement/makedata.tcl -ebc < ebc filename > datafile
xtclsh ../../sem_v3_2_0.srcs/sources_1/ip/sem_v3_2_0/sem_v3_2_0/implement/makedata.tcl -ebc sem_example.ebc datafile

If classification is enabled:

xtclsh ../../< component name >.srcs/sources_1/ip/< component name >/< component name >/implement/makedata.tcl -ebd < ebd filename > datafile
xtclsh ../../sem_v3_2_0.srcs/sources_1/ip/sem_v3_2_0/sem_v3_2_0/implement/makedata.tcl -ebd sem_example.ebd datafile

The command creates the vmf, bin and mcs files. The following figure shows the expected results:

Figure 12
Figure 12

Revision History
05/08/2012 - Initial Release

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44541 Soft Error Mitigation Controller - Release Notes and Known Issues for v1.1 to v3.4 N/A N/A
AR# 47202
Date Created 04/18/2012
Last Updated 05/20/2012
Status Active
Type Known Issues
IP
  • Soft Error Mitigation