This example design allocates 4K of BRAM attached to the M_AXI_GP0 and monitored by ChipScope tool. The software then treats the memory as a "shareable device" or "strongly-ordered," and a ChipScope shot provides the distance between the SEV instruction and the first BVALID signal on the AXI port for LATENCY.
Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000. A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.
It is up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill his needs. Limited support is provided by Xilinx on these Example Designs.
|Design Type||PS and PL|
|CPUs||Single CPU @ 720MHz|
|PL Cores||BRAM, CHIPSCOPE|
|Xilinx Tools Version||EDK 14.1|
|Other details||FCLK @ 150MHz|
|Base Address||Size||Bus Interface|
Archived XPS project.
|code_latency.c||Snippet of code.|
Step by Step Instructions
Strongly-ordered or Shareable device does not change the LATENCY.
Enabling the CACHE (L1 and L2) affects the LATENCY.
|Boards & Kits||