UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47266

Zynq-7000 Example Design - CPU latency to access an AXI Slave using Master AXI GP

Description

This example design allocates 4K of BRAM attached to the M_AXI_GP0 and monitored by ChipScope tool. The software then treats the memory as a "shareable device" or "strongly-ordered," and a ChipScope shot provides the distance between the SEV instruction and the first BVALID signal on the AXI port for LATENCY.

Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000. A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.

It is up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill his needs. Limited support is provided by Xilinx on these Example Designs.

Implementation Details
Design TypePS and PL
SW TypeStandalone
CPUsSingle CPU @ 720MHz
PS FeaturesMMU
PL CoresBRAM, CHIPSCOPE
Boards/ToolsZC702
Xilinx Tools VersionEDK 14.1
Other detailsFCLK @ 150MHz
Address Map
Base AddressSizeBus Interface
BRAM0x412000004KS_AXI
Files Provided
zc702_bram_archive.zip
Archived XPS project.
code_latency.cSnippet of code.
Block Diagram

 

Solution

Step by Step Instructions

  1. Import the archived design into XPS and export to SDK.
  2. In SDK create a Hello World example.
  3. Modify the Hello World example to include the snippet of C code.
  4. Program the PL using the BITSTREAM generated by XPS.
  5. Setup ChipScope tool to trigger on the EVENTO signal.
  6. Run the application.
  7. Measure the latency as the time between the rising edge of EVENTO and the BVALID signal on the AXI MASTER Interface.


Expected Results

Strongly-ordered or Shareable device does not change the LATENCY.

Enabling the CACHE (L1 and L2) affects the LATENCY.

 

 

 

Latency

Type

Cache

FCLK cycles

CPU cycles

Time (nS)

Strongly-ordered

Disabled

11

53

74

Strongly-ordered

Enabled

6

29

40

Shareable device

Disabled

11

53

74

Shareable device

Enabled

6

29

40

Attachments

Associated Attachments

Name File Size File Type
zc702_bram_archive.zip 2 MB ZIP
code_latency.c 1 KB C

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51779 Zynq-7000 AP SoC - Example Designs and Tech Tips N/A N/A
AR# 47266
Date 11/08/2017
Status Active
Type General Article
Devices
  • Zynq-7000
Tools
  • EDK - 14.1
Boards & Kits
  • Zynq-7000 SoC ZC702 Evaluation Kit
Page Bookmarked