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AR# 47296

14.x CORE Generator - Known Issues

Description

This answer record contains a list of known issues involving the CORE Generator tool in the 14.x ISE Design Suite release(s).

For IP-specific information, see the Xilinx Intellectual Property page.

Solution

Outstanding Known Issues in ISE Design Suite 14.7

(Xilinx Answer 20780) - CORE Generator - "ERROR:coreutil:195 - Could not create Java virtual machine"
(Xilinx Answer 21955) - An error occurred while running Java (possibly due to memory limitations)
(Xilinx Answer 24389) - The tab outlines of the IP views (View by function/name/Generated) are not visible on Windows XP 64-bit
(Xilinx Answer 32251) -"ERROR:coreutil:424" and "ERROR:sim:57" when using network drive
(Xilinx Answer 32412) - Error message displays when customizing IP over Xwin32"X, " Error: BadWindow (invalid Window parameter) 3"
(Xilinx Answer 35374) - "WARNING:sim:541 - Could not import file 'my_core.xco' during project migration."
(Xilinx Answer 40559) - Project Navigator needs to be closed and re-opened before the user IP repository changes will be seen
(Xilinx Answer 40736) - Using "Create Netlist Wrapper with IO pads" option causes some cores not to generate
(Xilinx Answer 43131) - Schematic symbol for some cores are not created or created with undesired size
(Xilinx Answer 45386) - IP Cores fail to generate when the project is accessed through a symbolic link
(Xilinx Answer 45457) - CORE Generator tool does not inform user that a Padded Netlist will not be created for source code core
(Xilinx Answer 45458) - Resetting MIG IP core in the PlanAhead tool deletes all of the MIG core files
(Xilinx Answer 45485) - Setting both Verilog and VHDL output languages to "false" results in cryptic error
(Xilinx Answer 45849) - Upgrading MIG core to latest version does not work
(Xilinx Answer 45851) - Error not flagged for FIR v6.2 when coefficient is not negative-symmetric
(Xilinx Answer 45864) - Padded netlist generation fails for Multgen and Ethernet_Statistics cores
(Xilinx Answer 53041) - Core generation hangs when about 1GByte of memory is available for the CORE Generator tool Article
(Xilinx Answer 55868) - Generation of Serial RapidIO 5.x IP core fails if the JAVA verbose switch is used
(Xilinx Answer 55875) - ERROR:HDLCompiler:104 occurs when importing XCO of 3rd party into the an ISE project

Known Issues Resolved in ISE Design Suite 14.7
None listed

Known Issues Resolved in ISE Design Suite 14.6
None listed

Known Issues Resolved in ISE Design Suite 14.5

(Xilinx Answer 53695) - IP cores cannot be created when using a 14.4 WebPACK tools install 

Known Issues Resolved in ISE Design Suite 14.4
None listed

Known Issues Resolved in ISE Design Suite 14.3

(Xilinx Answer 45359) - Importing an XCO file with an incompatible device compared with the current project results in a fatal error
(Xilinx Answer 51134) - ChipScope core fails to generate on Windows platform due to 260 character limit even though the project path does not seem extremely long
(Xilinx Answer 55843) - Closing and reopening a CORE Generator project after changing the HDL target language greys out (disables) available cores in catalog

AR# 47296
Date Created 05/07/2012
Last Updated 11/01/2013
Status Active
Type Known Issues
Tools
  • ISE Design Suite - 14.1