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MIG 7 Series DDR2/DDR3 - Synplicity fails to compile VHDL designs
Version Found: v1.5
Version Resolved and other Known Issues: See(Xilinx Answer 45195).
Synplicity fails to compile the MIG 7 Series DDR2/DDR3 VHDL designs.
The following error message is received:
@E: CD629 :"./mig_7series_v1_5/user_design/rtl/phy/ddr_phy_top.vhd":625:5:625:6|Failed to evaluate generic ctl_bank
This is an issue with the Synplify Pro VHDL compiler and is scheduled to be fixed in a future version of Synplify.
There is no workaround for Synplify, so XST must be used as a workaround if the VHDL design is required.
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