Xilinx Vivado HLS Solution Center
The Vivado HLS Solution Center is available to address all questions related to the tool.
Whether you are learning how to use the tool or troubleshooting a problem, use the Solution Center to guide you to the right information.
Design Assistant
Xilinx Vivado HLS Solution Center - Design Assistant
The Design Assistant walks you through the recommended design flow for Vivado HLS.
The Design Assistant not only provides useful design and troubleshooting information, but also points you to the exact documentation you need to read to help you design efficiently with Vivado High-Level Synthesis.
Note: This answer record is part of the Xilinx Vivado HLS Solution Center (Xilinx Answer 47428).
The Xilinx Vivado HLS Solution Center is available to address all questions related to Vivado HLS.
Free video trainings are available at the Xilinx Training site:
Vivado High-Level Synthesis Training
Directive Behaviors
| (Xilinx Answer 60923) | Design Assistant for Vivado HLS : Understanding the Vivado HLS Design Flow |
| (Xilinx Answer 60924) | Design Assistant for Vivado HLS : C Code and Vivado HLS |
| (Xilinx Answer 60925) | Design Assistant for Vivado HLS : Design Analysis and Optimization |
| (Xilinx Answer 60926) | Design Assistant for Vivado HLS : RTL Verification |
| (Xilinx Answer 60927) | Design Assistant for Vivado HLS : Integrating HLS IP into the System |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 44786 | AutoESL - Sharing of internal AP_STREAMs and scope | N/A | N/A |
| 47509 | Vivado HLS 2012.2: Why is the AP_ready port not written out? | N/A | N/A |
| 50929 | AutoESL - Zynq SoC Design Example with AXI-DMA Core for Data Transfer | N/A | N/A |
| 59678 | Vivado HLS 2013.4, 2014.1: FFT, FIR designs and examples: incorrect values are reported and are not updated | N/A | N/A |
| 60923 | Design Assistant for Vivado HLS : Understanding the Vivado HLS Design Flow | N/A | N/A |
| 60924 | C Code and Vivado HLS | N/A | N/A |
| 60925 | Vivado HLS : Design Analysis and Optimization | N/A | N/A |
| 60926 | Vivado HLS : RTL Verification | N/A | N/A |
| 60927 | Vivado HLS : Integrating HLS IP into the System | N/A | N/A |
| 61063 | Vivado HLS 2014.2: Debug Guide for investigating C/RTL co-simulation issues | N/A | N/A |
Documentation
Xilinx Vivado HLS Solution Center - Documentation
Please refer to the following documentation when using Vivado High-Level Synthesis.
Note: This answer record is part of the Xilinx Vivado HLS Solution Center (Xilinx Answer 47428).
The Xilinx Vivado HLS Solution Center is available to address all questions related to Vivado HLS.
User Guides
Vivado High-Level Synthesis User Guide (UG902)
https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug902-vivado-high-level-synthesis.pdf
Vivado Design Suite Tutorial: High-Level Synthesis (UG871):
https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug871-vivado-high-level-synthesis-tutorial.pdf
Documentation Navigator Design Hub for Vivado HLS
A Design Hub for Vivado HLS is available inside Xilinx Documentation Navigator (Documentation Navigator).
Xilinx Documentation Navigator provides access to all Xilinx documentation.
The Design Hub tab contains a section on High-Level Synthesis which contains links to all Vivado High-Level Synthesis documentation, QuickTake training videos and Application Notes.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 59626 | Vivado HLS 2014.1: How do I compile with Microsoft Visual Studio? | N/A | N/A |
| 61343 | Vivado HLS: XAPP1209 v1.0 download link for design file does not work. | N/A | N/A |
Top Issues
Xilinx Vivado HLS Solution Center - Top Issues
This answer record covers current known issues related to the Vivado HLS tool.
This answer record is part of the Xilinx Vivado HLS Solution Center; see (Xilinx Answer 47428).
The Xilinx Vivado HLS Solution Center is available to address all questions related to Vivado HLS tools.
Top Issues
| (Xilinx Answer 43271) | AutoESL - RTL Implementation results in "@E [IMPL-4] 'autoimpl' failed: 'xtclsh' cannot be found. Please check your PATH variable." |
| (Xilinx Answer 51042) | Vivado HLS - RTL export result in "@E [IMPL-28] Failed to generate IP." or "@E [IMPL-4] 'xtclsh' cannot be found. Please check your PATH variable." |
| (Xilinx Answer 50152) | Vivado HLS - Java 2 Platform Standard Edition binary has stopped working |
| (Xilinx Answer 50501) | Vivado HLS - Running Verilog or VHDL simulation with ModelSim results in errors |
Vivado HLS Known Issues
For Vivado HLS known issues, use the "Search" box on the upper left corner of the Xilinx Support Page.
A filter can be applied to sort out known issues specific to a version. There are also issues that might affect multiple tool versions.