Solution
Introduction
For installation instructions for this release, see:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements, see:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP 7 Series FPGAs Transceivers Wizard v2.1 solution. For the latest core updates, see the product page at:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/7-series_fpga_transceivers_wizard.html
New Features
ISE Design Suite
- ISE 14.1 software support
- Support for GTP Transceiver
- Support for PCIE Gen1/Gen2 protocol for GTX and GTH Transceiver
- Enhanced Example Design for GTX and GTH
- Support for Initial ES for GTH
Vivado Design Suite
- 2012.1 software support
- Support for GTP Transceiver
- Support for PCIE Gen1/Gen2 protocol for GTX and GTH Transceiver
- Enhanced Example Design for GTX and GTH
- Support for Initial ES for GTH
Supported Devices
ISE Design Suite
The following device families are supported by the core for this release.
Vivado Design Suite
Resolved Issues
ISE Design Suite
- Enhancements to Example Design for GTX and GTH
Description: A new module has been added for Initialization and Reset in the Example Design for GTX and GTH. This module demonstrates the initialization procedure to be followed as described in UG769.
Version(s) Fixed:
CR 640548
- Support for Initial ES - GTH
Description: Port and Attribute Settings are updated to support GTH Initial ES
Version(s) Fixed:
CR 652365
- New Protocol Support for GTX
Description: Protocol templates are added for: HD-SDI, 3G-SDI, 6G-SDI.
Please note that these templates have not been tested on hardware.
- New Protocol Support for GTH
Description: Protocol templates are added for: XAUI, RXAUI, OTL3.4, 1000BASE-X PCS/PMA, QSGMII, CPRI.
Please note that these templates have not been tested on hardware.
- New Protocol Support for GTP
Description: Protocol templates are added for: Display Port, CPRI, 1000BASE-X PCS/PMA, QSGMI, V-by-One, HD-SDI, 3G-SDI, 6G-SDI, RXAUI, XAUI.
Please note that these templates have not been tested on hardware.
Vivado Design Suite
- Enhancements to Example Design for GTX and GTH
Description: A new module has been added for Initialization and Resetin the Example Design for GTX and GTH. This module demonstrates theinitialization procedure to be followed as described in UG769.
Version(s) Fixed:
CR 640548
- Support for Initial ES - GTH
Description: Port and Attribute Settings are updated to support GTH Initial ES
Version(s) Fixed:
CR 652365
- New Protocol Support for GTX
Description: Protocol templates are added for: HD-SDI, 3G-SDI, 6G-SDI.
Please note that these templates have not been tested on hardware.
- New Protocol Support for GTH
Description: Protocol templates are added for: XAUI, RXAUI, OTL3.4, 1000BASE-X PCS/PMA, QSGMII, CPRI.
Please note that these templates have not been tested on hardware.
- New Protocol Support for GTP
Description: Protocol templates are added for: Display Port, CPRI, 1000BASE-X PCS/PMA, QSGMI, V-by-One, HD-SDI, 3G-SDI, 6G-SDI, RXAUI, XAUI.
Please note that these templates have not been tested on hardware.
Known Issues
ISE Design Suite
The following are known issues for v2.1 of this core at time of release:
- Support for GTP Transceiver
Description:
a) ISE Simulator Support for GTP is disabled in 14.1.
b) Implementation using Synplify is not supported in 14.1
c) Timing Simulation is disabled in 14.1
d) User can expect issues during Place and Route phase of Implementation due to issues in Tool flow
Vivado Design Suite
The following are known issues for v2.1 of this core at time of release:
- Support for GTP Transceiver
Description:
a) ISE Simulator support for GTP is disabled in 14.1.
b) Implementation using Synplify is not supported in 14.1
c) Timing Simulation is disabled in 14.1
d) User can expect issues during Place and Route phase of Implementation due to issues in Tool flow
The most recent information, including known issues, workarounds, and resolutions for this version is provided in the IP Release Notes Guide located at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf
Technical Support
To obtain technical support, create a WebCase. Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.
Other Information
Core Release History
Date By Version Description
================================================================================
04/24/2012 Xilinx, Inc. 2.1 ISE 14.1 and Vivado 2012.1 support
01/18/2012 Xilinx, Inc. 1.6 ISE 13.4 support
10/19/2011 Xilinx. Inc. 1.5 ISE 13.3 support
06/22/2011 Xilinx, Inc. 1.4 ISE 13.2 support
03/01/2011 Xilinx, Inc. 1.3 ISE 13.1 support
================================================================================