| Impact: | Minor, it affects usage of SS 0 in master mode. |
| Work-arounds: | Please see Article Details section. |
| Configurations Affected: | Systems using the SPI controller via the MIO interface. |
| Device Revision(s) Affected: | Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences |
When interfacing via MIO or EMIO:
1. Do not enable the SPI SS0 signal on any of the MIO pins.
2. Configure the EMIO SPI SS0 port signal in the MHS file so its an output and the SS input is tied to net_vcc:
Note: the ISE 14.1 default settings connect the EMIO SS0 output to the input and causes the controller to reset when the controller asserts SS 0.
Note for Production Silicon: In master mode, connect SS0 to Vcc if SS0 is not used. This is important because the controller snoops this signal in master mode to detect a multi-master mode situation; if SS0 is a logic Low, then the controller will assume multi-master mode and issue a Mode_Fail interrupt. Vcc is not the default setting for an unused SS0 signal in Vivado 2013.2.
| AR# 47511 | |
|---|---|
| Date | 05/23/2018 |
| Status | Active |
| Type | Design Advisory |
| Devices |
|