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AR# 47511

Zynq-7000 AP SoC, SPI - In Master Mode on MIO, the SPI Controller Resets Itself when the SS0 Signal Asserts


When the SPI controller is configured as a master, the SS0 signal is an output. The unused input signal from the MIO/EMIO multiplexer must remain deasserted. When using an MIO interface, route the SS0 controller signals to the EMIO interface and assign the EMIO SS0 input signal to net_vcc (this may not be the default setting).


Impact: Minor, it affects usage of SS 0 in master mode.
Work-arounds: Please see Article Details section.
Systems using the SPI controller via the MIO interface.
Device Revision(s) Affected: Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences


When interfacing via MIO or EMIO:

1. Do not enable the SPI SS0 signal on any of the MIO pins.

2. Configure the EMIO SPI SS0 port signal in the MHS file so its an output and the SS input is tied to net_vcc:

  • PORT processing_system7_0_SPI0_SS_O_pin = processing_system7_0_SPI0_SS_O, DIR = O
  • PORT SPI0_SS_O = processing_system7_0_SPI0_SS_O
  • PORT SPI0_SS_I = net_vcc

Note: the ISE 14.1 default settings connect the EMIO SS0 output to the input and causes the controller to reset when the controller asserts SS 0.

Note for Production Silicon:  In master mode, connect SS0 to Vcc if SS0 is not used. This is important because the controller snoops this signal in master mode to detect a multi-master mode situation; if SS0 is a logic Low, then the controller will assume multi-master mode and issue a Mode_Fail interrupt. Vcc is not the default setting for an unused SS0 signal in Vivado 2013.2.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 47511
Date 08/21/2013
Status Active
Type Design Advisory
  • Zynq-7000
  • XA Zynq-7000
  • Zynq-7000Q