2. Support
  3. AR# 4752: M1.5:Trce: Does not produce the custom delay information from input pad through asynchronous CLR/PRE to output of a Flip flop.
  4. AR# 47520: Zynq-7000 SoC, SMC - NAND ECC Status Register can Incorrectly Report a Failure for One Clock Cycle

AR# 47520

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Zynq-7000 SoC, SMC - NAND ECC Status Register can Incorrectly Report a Failure for One Clock Cycle

Description

The software might trigger an abort that can lead to the ecc_last_status value being incorrectly shown for one cycle after the ecc_status bit has gone Low.

The software must re-read the ecc_last_status whenever it detects a non-zero value.

Solution

Impact:Trivial, re-read ECC status, as necessary.
Work-around:If software reads a non-zero value from the ecc_last_status bits of the ecc_status register, then the value in the ecc_status register must be read for a second time to ensure the correct value is returned.
Configurations Affected:Systems that use ECC with NAND.
Device Revision(s) Affected:All, no plan to fix. See (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences


The ecc_status register contains a 2-bit ecc_last_status value that reports the success or failure of the previous ECC operation. The ecc_last_status value is only valid once the ecc_status bit in the same register has gone low, indicating the ECC is idle. All the failure modes reported in ecc_last_status are due to software errors where the software has made a mistake:

  1. Case where ecc_last_status = 01: Software tried to start an ECC operation at an address that is out-of-range or not correctly aligned to a 512-byte boundary.
  2. Case where ecc_last_status = 10: Software provided an incorrect amount of data for the ECC operation.
  3. Case where ecc_last_status = 11: Software programmed the controller to not jump around the page to write the ECC codes to memory and then failed to provide an entire page of data.

If the driver makes one of the above mistakes, the abort code is correctly reported. However, if it then performs a successful sequence, the ecc_last_status value will incorrectly show the same abort for 1 cycle after ecc_status bit has gone Low.

Impact Details

During normal operation, it is not expected that the NAND software will ever cause any of the abort codes reported by the ecc_last_status bits. Only false failures (never false passes) can be reported as a result of this issue so there are no-implications for data-integrity or for ECC operation when the data is read back.

The implications will come from how the softwarereacts to the abort code. However, suitable error handling must be in place as this errata can only occur after a real abort has occurred and been dealt with by software.

Work-around Details

If software reads a non-zero value from the ecc_last_status bits of the ecc_status register then the value in the ecc_status register must be read for a second time to ensure the correct value is returned.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 47520
Date 06/13/2018
Status Active
Type Design Advisory
Devices
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