AR# 47555


Zynq-7000 SoC, APU - Imprecise Abort Can Be Reported Twice On Non-Cacheable Reads


When the CPU has two outstanding read memory requests to a device or non-cacheable normal memory region, and the first one receives an imprecise external abort, then the second access can falsely report an imprecise external abort, too. In practice, imprecise aborts are usually unrecoverable failures and include a processor reset or whole system reboot, so the second abort would have not impact.


Impact:Trivial. Unrecoverable errors are catastrophic and almost always result in a system reset by software.
Work-around:No practical work-around.
Configurations Affected: Systems that use one or both ARM processors.
Device Revision(s) Affected:All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences.


There is no practical work-around.

Impact Details

When the issue occurs, a second, spurious imprecise abort may be reported to the core when it should not. In practice, the failure is not expected to cause any significant issues to the system because imprecise aborts are usually unrecoverable failures. Because the spurious abort can only happen following a first imprecise abort, either the first abort is ignored and the spurious abort is then ignored too, or it is acknowledge and probably generates a critical failure in the system, like a processor reset or whole system reboot.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 47555
Date 05/23/2018
Status Active
Type Design Advisory
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