Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)
The ISE Design Suite CORE Generator tool does not support SSIT devices.
The ISE design tools do not support SSIT devices. Although enabled, this flow is not supported and users should use the Vivado tool flow when targeting SSIT devices. This is a known issue and will be fixed in a future release of the core.
NOTE: The latter issue, regarding the core being enabled for SSIT devices in the CORE Generator tool, described above has now been resolved. However, to use SSIT devices, you must use theVivado tool flow.
Revision History
12/17/2012 - Added note about issue being resolved.
05/08/2012 - Initial release
Note: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 47441 | Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 | N/A | N/A |
| AR# 47612 | |
|---|---|
| Date | 12/17/2012 |
| Status | Active |
| Type | Known Issues |
| IP |
|