AR# 47623


Vivado DSP Tools - System Generator for DSP 2012.1 - Why do I get critical warnings on pin locations and constraints not applied for a model in a design with mutiple unique SysGen submodules?


If a model is instantiated along with another model, critical warnings are given regarding the pins even though the constraint syntax is exactly the same in the XDC files for the single model, and the two unique models.

Critical warnings occur for each Pin Loc similar to the following:

[PlanAhead 1398] There are no top level ports directly connected to pins 'clk', returning pins matching pattern 'clk' for cell 'u_mac_fir'. ["C:\ATEST\V2012_1\p.15xc\VHDproj\VHDproj.srcs\sources_1\dsp\PinsLocked\sysgen\mac_fir_cw.xdc":16]

[Netlist 69] Cannot set property 'LOC', because the property does not exist for objects of type 'pin'. ["C:\ATEST\V2012_1\p.15xc\VHDproj\VHDproj.srcs\sources_1\dsp\PinsLocked\sysgen\mac_fir_cw.xdc":16]

However, the XDC constraints are exactly the same for both the multiple unique model and the single model cases.

For example:

set_property LOC AF16 [get_ports clk]
set_property LOC AD14 [get_ports {data_in1[1]}]
set_property LOC AD15 [get_ports {data_in1[0]}]
set_property LOC AD16 [get_ports {data_in2[1]}]
set_property LOC AD17 [get_ports {data_in2[0]}]


The LOC constraints should only be placed in the top level XDC file.

For System Generator for DSP Release Notes from other versions, see (Xilinx Answer 29595).

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AR# 47623
Date 02/07/2013
Status Active
Type Known Issues
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