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AR# 50064

7 Series FPGA GTH Transceiver RXOUTCLK Port in Initial ES Silicon

Description

This answer record discusses the RXOUTCLK port issue for line rates higher than 8.5 Gb/s in the 7 Series FPGA GTH Transceivers Initial ES silicon and its implications on different use cases.

Solution

For Initial ES GTH transceiver line rates higher than 8.5 Gb/s, when the RXOUTCLK port is configured to use the RXOUTCLKPCS or RXOUTCLKPMA path, it can exhibit a phase jump of up to two UI of the line rate. Please refer to the following section for implications on specific use modes.

Buffer use mode:

For buffer use mode, the RX elastic buffer can absorb the two UI jump of the RXOUTCLK. However, for designs in the fabric FPGA, this two UI phase jump needs to be accounted for to avoid data corruption. This can be addressed by specifying a INPUT_JITTER timing constraint of two UI of jitter on the RXOUTCLK clock period. For data rates above 8.5 Gb/s, this translates to 10% of the period.

Buffer bypass mode:

In the buffer bypass mode, the RXOUTCLK port cannot be used because of this phase jump issue for GTH transceiver line rates higher than 8.5 Gb/s. As a result, RX buffer bypass cannot be used.

AR# 50064
Date Created 05/24/2012
Last Updated 11/28/2012
Status Active
Type General Article
Devices
  • Virtex-7
  • Virtex-7 HT