2. Support
  3. AR# 5035: M1.5 Spartan mapper can not fit design that fit in M1.4.
  4. AR# 50359: Vivado IP Flows - How do I generate the structural simulation model for an IP core in a Vivado project?

AR# 50359

Vivado IP Flows - How do I generate the structural simulation model for an IP core in a Vivado project?

Description

When generating an IP core from the IP Catalog within a Vivado project, it does not appear to be possible to choose to generate structural simulation models as opposed to the default behavioral simulation models.

How do you switch to structural models?

Solution

There are currently three options on how to achieve this as follows:

  • Create a separate project for the IP, synthesize and use write_verilog or write_vhdl to get the structural netlist for the core. You can use the Manage IP flow in the Vivado tool to generate the separate IP core project.
  • Another option is to set the IP core as the top level in the overall project, synthesize it, and write the verilog or VHDL file and add it to the project; this way, you do not need to create a separate project or copy the original IP.
  • You can also use CORE Generator standalone with the CORE Generator project settings set to structural simulation model, and then import the sources into the Vivado tool.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
60121 2014.1 Vivado - Modules in the library "XilinxCoreLib" are not recognized in the design hierarchy when "Automatic Compile Order" is selected N/A N/A
AR# 50359
Date 02/18/2016
Status Active
Type General Article
Devices
Tools
IP