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  1. Xilinx - All Programmable
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  3. AR# 50499: 14.2 EDK - Toggling PS_SRST_B does not configure PL when booting from SD or QSPI using BOOT.bin

AR# 50499

14.2 EDK - Toggling PS_SRST_B does not configure PL when booting from SD or QSPI using BOOT.bin

Description

There is a reboot status register that is not being cleared after initial boot of the FSBL, Bitstream, and U-BOOT. On first boot up, the register is set to 0 for the zero partition, which is where the bitstream is located. Then, the register is set to 1 for the first partition, which is where U-BOOT is located. At FSBL handoff, the register is not cleared and is stuck at 1. If PS_SRST_B toggles, the FSBL bypasses the "zero" partition (configuration of the PL) and immediately loads the "one" partition (U-BOOT).

Solution

Modify the function void ClearFSBLIn(void) in main.c in the FSBL:

void ClearFSBLIn(void) {
160;FsblOut32(REBOOT_STATUS_REG,
(FsblIn32(REBOOT_STATUS_REG) & ~FSBL_IN_MASK) &
~PARTITION_NUMBER_MASK); }

Currently, the plan is to fix this in 14.3.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
52540 Zynq-7000 AP SoC - Frequently Asked Questions N/A N/A
AR# 50499
Date 10/24/2012
Status Active
Type Known Issues
Devices
  • Zynq-7000
Tools
  • EDK - 14.1
  • EDK - 14.2