We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 50499

14.2 EDK - Toggling PS_SRST_B does not configure PL when booting from SD or QSPI using BOOT.bin


There is a reboot status register that is not being cleared after initial boot of the FSBL, Bitstream, and U-BOOT. On first boot up, the register is set to 0 for the zero partition, which is where the bitstream is located. Then, the register is set to 1 for the first partition, which is where U-BOOT is located. At FSBL handoff, the register is not cleared and is stuck at 1. If PS_SRST_B toggles, the FSBL bypasses the "zero" partition (configuration of the PL) and immediately loads the "one" partition (U-BOOT).


Modify the function void ClearFSBLIn(void) in main.c in the FSBL:

void ClearFSBLIn(void) {

Currently, the plan is to fix this in 14.3.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
52540 Zynq-7000 AP SoC - Frequently Asked Questions N/A N/A
AR# 50499
Date 10/24/2012
Status Active
Type Known Issues
  • Zynq-7000
  • EDK - 14.1
  • EDK - 14.2