The 7 series FPGAs data sheets state:
The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on.
The 7 series FPGAs contain a pin called PUDC_B. When PUDC_B is Low, internal pull-up resistors are enabled on each SelectIO pin. When PUDC_B is High, internal pull-up resistors are disabled on each SelectIO pin. The state of this pin effects the state of the I/O from power-on until configuration completes. Therefore, the I/Os will be 3-stated after power-on when PUDC is High.
The state of the I/O prior to the rails being powered is not guaranteed.
NOTE: Due to the presence of the clamp diode, if the I/Os are driven before Vcco powered this will reverse bias the Vcco rail. For further information, see (Xilinx Answer 45985).