Writing and reading through DRP port the GTX RX_DFE_KL_CFG2 parameter returns the wrong results because the DRP addresses are incorrect in version v1.5 of the 7 Series FPGA GTX/GTH Transceivers User Guide (UG476).
Instead, please use the following DRP address:
RX_DFE_KL_CFG2[3:0] maps to Address 0x074 [3:0]
RX_DFE_KL_CFG2[8:4] maps to Address 0x074 [15:11]
RX_DFE_KL_CFG2[12:9] maps to Address 0x07F [3:0]
RX_DFE_KL_CFG2[17:13] maps to Address 0x07F [14:10]
RX_DFE_KL_CFG2[26:18] maps to Address 0x083 [15:7]
RX_DFE_KL_CFG2[31:27] maps to Address 0x08C [7:3]
This is corrected in version v1.6 of the user guide.