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SPI-4.2 v12.2 - Release Notes and Known Issues for 2012.2 release
This Release Notes and Known Issues Answer Record is for the SPI-4.2 (POS-PHY L4) v12.2 Core for 2012.2 release, and contains the following information:
- New Features
- Supported Devices
- Resolved Issues
- General Information
- Known Issues
For installation instructions, general CORE Generator software known issues, and design tools requirements, see the IP Release Notes Guide at:
- Vivado 2012.2 software support
- Virtex-7, Virtex-7 HT/XT and Kintex-7FPGA
- XDC Timing assertions need to be updated to avoid slack violations onMAX delay constraints. The XDC file has been updated.
- When running implementation on the SPI-4.2 IP example design, you get an ERROR: [Place-497] Placer failed with error: 'IO Clock Placer failed'. The issue has been fixed.
- The IP does not support behavioral simulation with the Vivado Simulator in 2012.2. To work around this issue, use the structural simulation flow documented in (Xilinx Answer 50908).
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Associated Answer Records
- SPI-4 Phase 2 Interface Solutions