Description

• New Features
• Supported Devices
• Resolved Issues
• General Information
• Known Issues

For installation instructions, general CORE Generator software known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

• Vivado 2012.2 software support

• Virtex-7, Virtex-7 HT/XT and Kintex-7FPGA

• XDC Timing assertions need to be updated to avoid slack violations onMAX delay constraints. The XDC file has been updated.
• CR 655763
• When running implementation on the SPI-4.2 IP example design, you get an ERROR: [Place-497] Placer failed with error: 'IO Clock Placer failed'. The issue has been fixed.
• CR 654538

• The IP does not support behavioral simulation with the Vivado Simulator in 2012.2. To work around this issue, use the structural simulation flow documented in (Xilinx Answer 50908).

Linked Answer Records

Associated Answer Records