AR# 51139

VC707 UG885 (v1.0) - FPGA to LCD Header Connections

Description

The VC707 Evaluation Board for the Virtex-7 FPGA User Guide v1.0 (UG885), Table 1-23 on page 44, lists the FPGA to LCD Header Connections. FPGA pin AR42 is listed twice.

What are the correct FPGA to LCD Header Connections for this kit?

Solution

LCD_RW_LS is associated with pin AR42.

LCD_DB4_LS is associated with pin AT42.

Table 1-23 of UG885 should read as shown below:

This has been updated in v1.1 of the VC707 Evaluation Board for the Virtex-7 FPGA User Guide (UG885).

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Linked Answer Records

Master Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
45382	Virtex-7 FPGA VC707 Evaluation Kit - Known Issues and Release Notes Master Answer Record	N/A	N/A

AR# 51139
Date	09/17/2013
Status	Active
Type	General Article
Boards & Kits	Virtex-7 FPGA VC707 Evaluation Kit

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