We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 51151

14.2 EDK, axi_7series_ddrx - "ERROR:EDK:3458 - In the core DDR, the ratio of clock frequencies is invalid for the ports clk and freq_refclk..."


When using the AXI_7series_ddrx controller in 1/4 clocking mode, the following error occurs:

Performing Clock DRCs...
ERROR:EDK:3458 - In the core ddr, the ratio of clock frequencies is invalid for
   the ports clk and freq_refclk
ERROR:EDK:3365 - Clock frequency ratio requirements not met in IP : ddr
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/system_main_clock_generator_wrapper.ngc] Error 2

How do I resolve this issue?


This issue is caused by an invalid DRC that must be adjusted.

A patch is attached to this answer record below.

To install the patch, extract it into the projects pcore/ directory and restart XPS.

This issue is fixed in XPS 14.3/2012.3.


Associated Attachments

Name File Size File Type
ar51151.zip 19 KB ZIP
AR# 51151
Date 10/15/2014
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Zynq-7000
  • MIG 7 Series
Page Bookmarked