UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 51432: 14.2 EDK - ChipScope AXI Monitor - Error when Connecting to a Streaming Interface

AR# 51432

14.2 EDK - ChipScope AXI Monitor - Error when Connecting to a Streaming Interface

Description

When trying to connect the ChipScope AXI Monitor to a streaming interface, the following errors occurs:

ERROR:EDK - Could not connect MONITOR chipscope_axi_monitor_0's RESET MON_AXI_ARESETN to INSTANCE <peripheral>'s RESET port as the latter is itself un-connected
ERROR:EDK - Could not connect MONITOR chipscope_axi_monitor_0's RESET MON_AXI_ACLK to INSTANCE <peripheral>'s RESET port as the latter is itself un-connected

This error occurs for any peripheral connected to a streaming interface, including those created with the Create/Import Peripheral Wizard.

Solution

This error occurs because the ChipScope AXI Monitor clock and reset ports are associated with the AXI4-Stream clock and reset ports. If these ports do not exist for the AXI4-Stream interface, the AXI Monitor is not able to populate with a clock and reset connection.

There are a few possible workarounds for this issue.

  • Override the connection of the AXI Monitor's clock and reset ports
    • Modify system.mhs to include the MON_AXI_ARESETN port
    • Ensure that the resetsignal is the same as that of the debug target reset port

BEGIN <peripheral>
PARAMETER INSTANCE = <peripheral_0>
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE M_AXIS = <peripheral>_M_AXIS
BUS_INTERFACE S_AXIS = microblaze_0_M0_AXIS
PORT ACLK = clk_400_0000MHz
PORT ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN chipscope_axi_monitor
PARAMETER INSTANCE = chipscope_axi_monitor_0
PARAMETER HW_VER = 3.05.a
PARAMETER C_USE_INTERFACE = 1
BUS_INTERFACE MON_AXI_S = sdfsf_0_M_AXIS
PORT CHIPSCOPE_ICON_CONTROL = chipscope_icon_0_control0
PORT MON_AXI_ACLK=clk_400_0000MHz
PORT MON_AXI_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END
  • Use the ChipScope ILA core instead of AXI Monitor
    • For more information on how to use the ChipScope ILA core in XPS, please refer to DS299LogiCORE IPChipScope Pro Integrated Logic Analyzer (ILA)
  • Change the MPD of MicroBlaze by extending the BUSIF tags for the clock and reset to include the AXI4-S ports
    • Note: Do not modify the MicroBlaze MPD in the Xilinx Tools install directory
    • Copy the MicroBlaze core <root>:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_40_a and place it in the pcore folder of the project directory
    • In XPS, right-click microblaze_0 -> Delete Instance -> Delete instance but do not remove the nets -> OK
    • Project -> Rescan User Repository
    • In IP Catalog, expand Project Local PCores/Processor
    • Right-click microblaze -> Add IP -> Yes
    • Select pertinent configurations for the user design
    • Click Advanced -> Buses -> Number of Steam Links = 1 -> OK
    • User will make necessary connections and settings (XPS can do this automatically, but new LMB, BRAM, and BRAM CTRL instances will be created)
    • Make necessary connections
    • Project -> Run DRC to confirm that the error is gone
AR# 51432
Date 02/14/2013
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • EDK
IP
  • Embedded Processing
  • FPGA Features and Debug
Page Bookmarked