We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 51726

2014.1 Vivado HLS - Assert function permitted in C Synthesis and "Release Mode" of C Simulation.


Why do C Synthesis and the "Release Mode" of C Simulation allow assert?

Should assert be supported by "Debug Mode" only?


By default, assert is active in C Synthesis and in both "Release Mode" and "Debug Mode" in C simulation.

However, users can control the behavior of C Simulation by defining "DEBUG" or "NDEBUG" explicitly to control the tool's behavior, either by using "#define" or CFLAGS.

To control the behavior of C Synthesis, only CFLAGS of source files can be used.

Please note that assertions can inform High-Level Synthesis about the maximum range of variables, and how those assertions are used to produce more optimal hardware.

Refer to section "Using Assertions" of UG902 (page 383 in version 2014.1).

AR# 51726
Date 06/11/2014
Status Active
Type General Article
  • AutoESL
  • Vivado Design Suite - 2012.2