The issue here is that the Pcorecreated from System Generator makes HDL code that explicitly sets the parameters for id_width.
There aretwo possible workarounds for this issue:
1) Open the <ip_name>_axiw.vhd in the process directory seen below:
Changelines 67 to 71 from:
s_axi_arid(C_S_AXI_ID_WIDTH-1 downto 0) <= sg_s_axi_arid;
s_axi_awid(C_S_AXI_ID_WIDTH-1 downto 0) <= sg_s_axi_awid;
sg_s_axi_rid <= s_axi_rid(C_S_AXI_ID_WIDTH-1 downto 0);
sg_s_axi_bid <= s_axi_bid(C_S_AXI_ID_WIDTH-1 downto 0);
Once this is done,Rescan theUser Repository:
The IP should pass through the tools now without issue. It is likely you may get a Bitgen error if your System Generator pcore contains I/O portsthat have not been LOC'ed in the UCF.
2) Alternatively, there is a patch available for System Generator which can be requested through Xilinx Technical Support. Please open a Webcase to request the patch.