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AR# 5175

CPLD, XC9500XL/XV - What is the bus-hold (keeper) circuit?

Description

What is the "bus-hold" circuit, and how is it used?

Solution

CoolRunner-II

The bus-hold circuit exists in the IOB structure, and is used to hold the last known state of I/O until the next I/O value is available. It may be enabled or disabled on a pin-by-pin basis. For more information on this, consult (Xilinx Answer 14318). For information on the range of resistance, see (Xilinx Answer 16851).

XC9500XL/XV

The bus-hold (or the keeper circuit) is an architectural feature that was added to the XC9500XL/XV devices (it is not available in the XC9500 devices). This circuit exists in the IOB structure, and is used to hold the last known state of I/O until the next I/O value is available. It is roughly 25K ohm with a range of 15K to 70K (the lower range at lower temperatures). This is not controllable on a pin-by-pin basis. This setting described below affects the bus-hold circuit for the entire device.

The bus-hold circuit acts as a weak keeper on the I/O pins at all times, except in the following situations:

  • When the device is blank
  • During power-up/configuration cycle
  • During the INTEST command
  • When the device is in ISP mode
  • When disabled in software properties

5.1i and newer software:

To turn this feature off, highlight the "Fit" process, then go to Process -> Properties -> Basic tab, and set I/O Pin Termination to "Float."

4.1/4.2i:

To turn this feature off, select the "Disable BUSHOLD Circuit" option under the "Generate Programming File" process properties in Project Navigator. This option is available as of 4.1i Service Pack 2.

For additional information, see (Xilinx Answer 1536).

It is important to note that when the Bus Hold is disabled the "Half Latch" may still be present, more information on the half latch can be found in the CPLD I/O User Guide.

AR# 5175
Date Created 08/21/2007
Last Updated 11/25/2013
Status Active
Type General Article
Devices
  • CPLD Device Families
  • 9500XL