AR# 51838

Design Assistant for Vivado Synthesis - Help with SystemVerilog Support - Packages

Description

This answer record describes SystemVerilog Packages supported by Vivado Synthesis and also provides coding examples for them. These coding examples are attached to this answer record. The answer record also contains information related to known issues and good coding practices.

Note: Each coding example can be used to directly create a Vivado project. Please refer to the header in each source file for the SystemVerilog constructs covered in each example.

Solution

SystemVerilog Packages structures that are supported by Vivado Synthesis

Please refer to Table 1-1 at the end of this AR for the related coding examples.

Packages provide an additional way to share different constructs. They have similar behavior to VHDL packages. Packages can contain many things, for example, functions, tasks, types, enums. Packages are referenced in other modules by the import command.

Coding Examples for Packages

Table 1-1

Coding Example Name	Constructs Used
packages_example.zip	enum, logic data type and user-defined data type struct package automatic function and void function case statement always_ff procedural block operator: +, -, *, =

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Attachments

Associated Attachments

Name	File Size	File Type
packages_example.zip	1 KB	ZIP

Linked Answer Records

Master Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
51360	Design Assistant for Vivado Synthesis - Help with SystemVerilog Support	N/A	N/A

AR# 51838
Date	04/03/2013
Status	Active
Type	Solution Center
Tools	Vivado Design Suite

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