Version Found: v1.7
Version Resolved and other Known Issues: See (Xilinx Answer 45195).
The MIG 7 Series RLDRAM II Traffic Generator in the example design gets stuck after generating a long series of write commands.
When the command FIFO becomes full, the Traffic Generator incorrectly continues to send data until the data FIFO also becomes full and the traffic generator then becomes stuck.
To work around this issue, use the "user_wdfifo_full" signal instead of the delayed version "user_wdfifo_r" in example_top.v.
To implement the work around, open example_top.v and change Line 715 to: