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AR# 52636

14.3 EDK - How do I create custom IP with multiple AXI interfaces?


How do I create custom IP with multiple AXI interfaces? For example, a core that uses an AXI4-Lite and an AXI-Stream interface simultaneously.


Except for the AXI4 Master IPIF example, the Xilinx EDK Create Import (CIP) Wizard does not create multiple interface examples.

An overview of using multiple AXI interfaces manually can be accomplished by merging multiple example cores:

  1. Obtain single-interface examples by running the Xilinx EDK Create Import (CIP) Wizard, or templates from (Xilinx Answer 37425).
  2. Consider a new top level HDL. Instantiate all interface examples into one HDL file, in a normal HDL-design manner. Uniquify port and parameter names.
  3. Merge PAO files, removing duplicate library declarations. If created, add the new top-level HDL file to the PAO file.
  4. Merge the MPD sections from the examples into a single MPD file. Be careful to make the same uniquifications as were done to the top-level HDL. Also, uniquify the BUS_INTERFACE labels which group individual HDL ports into a single AXI interface.

A complex example for a multiple interface core can be found in the AXI_DMA core, which uses AXI4, AXI4-Lite, and AXI-Stream interfaces.

Note: Xilinx does not support User Custom IP, including the Custom IP mentioned above. To debug Custom AXI IP, AXI BFM can be used.

AR# 52636
Date 05/23/2013
Status Active
Type General Article
  • FPGA Device Families
  • EDK
  • AXI Lite IPIF
  • AXI Master Burst
  • AXI Master Lite
  • AXI Slave Burst