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AR# 52788

14.x TIMING: BUFGMUX - How can I propagate the desired PERIOD constraint through a BUFGMUX?


I have a BUFGMUX with 2 input clocks, the Timing Analyzer shows the calculations for the PERIOD constraint I do not want to propagate.

How can I force the tools to propagate the desired PERIOD constraint after the BUFGMUX?  


When a BUFGMUX has 2 input clock signals, it is necessary to verify that both input signals have a PERIOD constraint applied or propagated from a clocking element.

Then in order to propagate the desired PERIOD constraint through the BUFGMUX, the word PRIORITY must be added to the constraint.  

The input PERIOD constraints must be related for the PRIORITY keyword to impact the analysis correctly.

If the constraint is generated by a clocking element , it is possible that this constraint needs to be re-write by the customer adding the previous word (PRIORITY).

For instance, there is a BUFGMUX called MUX_UP with 2 input clocks (MUX_UP_1 & MUX_UP_1) and the desired PERIOD constraint after the BUFGMUX is "TS_clk_mux_up_1".

The following is an example of constraints applied to the BUFGMUX using the PRIORITY word: 

NET MUX_UP_1 TNM_NET = "clk_mux_up_1";
TIMESPEC "TS_clk_mux_up" = PERIOD "clk_mux_up" 8 ns HIGH 50% PRIORITY 1;
NET MUX_UP_2 TNM_NET = "clk_mux_up_2";
TIMESPEC "TS_clk_mux_up_2" = PERIOD "clk_mux_up_2" 3.33 ns HIGH 50%;


If for any reason, the PERIOD constraint is still not being applied after the BUFGMUX, the best option is to over-write the constraint with the desired PERIOD constraint at the output of the BUFGMUX.


NET MUX_AFTER TNM_NET = "clk_mux_after";
TIMESPEC "TS_clk_mux_after" = PERIOD "clk_mux_after" 8 ns HIGH 50% ;


AR# 52788
Date 07/08/2014
Status Active
Type Design Advisory
  • FPGA Device Families
  • ISE Design Suite